Array Structure, Manufacturing Method Thereof, Array Substrate and Display Device

ABSTRACT

An array structure and a manufacturing method thereof are disclosed. The method for manufacturing the array structure includes: forming a gate insulating layer on a substrate; and etching the gate insulating layer at a position corresponding to a source/drain signal access terminal to form a through-hole structure provided with an outward-inclined side wall in the gate insulating layer.

The application is a divisional of U.S. patent application Ser. No.14/409,316, filed on Dec. 18, 2014, which is a U.S. National Phase Entryof International Application PCT/CN2014/080453 filed on Jun. 20, 2014,designating the United States of America and claiming priority toChinese Patent Application No. 201310571411.1, filed on Nov. 15, 2013.The present application claims priority to and the benefit of theabove-identified applications and the above-identified applications areincorporated by reference herein in their entirety.

TECHNICAL FIELD

The present disclosure relates to the field of display technology, andin particular to an array structure, a manufacturing method thereof, anarray substrate based on the array structure, and a display device.

BACKGROUND

Currently, with the continuous improvement of the resolution of liquidcrystal display panels, particularly as for liquid crystal displaypanels of small dimension, the improvement of the resolution means theincrease of the quantity of pixels in unit length, namely PPI (pixelsper inch), and hence the quantity of leading wires within the same spaceincreases accordingly.

It is known to the inventor that, generally, the space for wiring isreduced as much as possible by adoption of alternate wiring for an IC(integrated circuit) to solve the problem of more and more IC pins. FIG.1 is a schematic view illustrating a gate layer and a source/drain (SD)metal layer which have wires thereof alternate with each other, 01represents the gate layer and 02 represents the SD metal layer. Thealternate wiring is performed through the gate layer and the SD metallayer, then through holes are formed in the gate layer and the SD metallayer by an exposing and etching process and finally wires are led outby an ITO (indium tin oxide) layer. The left side and the right side ofFIG. 2 are respectively sectional views of the gate layer and the SDmetal layer which have wires thereof alternate with each other. In FIG.2 a gate signal access terminal includes a gate electrode 01, a gateinsulating (GI) layer (03), a passivation (PVX) layer 04 and aconductive film 05 (e.g., an ITO layer) which are formed on a substrate00 in sequence. An SD signal access terminal includes the GI layer 03,an SD metal layer 02, the PVX layer 04 and the conductive film 05 whichare formed on the substrate 00 in sequence. As the gate signal accessterminal (pad) and the SD signal access terminal have differentstructures, the finally formed signal access terminals have differentheights, and hence poor contact between IC bonding pads and IC pins canbe caused. As illustrated in FIG. 3, the height of the conductive film05 in the SD signal access terminal is greater than that of theconductive film 05 in the gate signal access terminal. Height differenceoccurs between the conductive films 05 in the IC bonding padscorresponding to adjacent IC pins 07, and hence the contact areasbetween conductive balls 07 and the conductive films 05 in adjacent ICbonding pads are different and the applied forces are nonuniform. Thus,poor welding state can be caused and the conductivity can be reduced.

SUMMARY

The present disclosure provides a method for manufacturing an arraystructure, which method, before forming an SD metal layer on a GI layer,further includes: etching the GI layer at a position corresponding to anSD signal access terminal, and forming a through-hole structure in theGI layer.

Moreover, after etching the GI layer at the position corresponding tothe SD signal access terminal, the method further includes: forming theSD metal layer, a PVX layer and a conductive film in sequence on the GIlayer provided with the through-hole structure.

Furthermore, after forming the SD metal layer, the method furtherincludes: performing a same etching to the SD metal layer at a positioncorresponding to the through-hole structure as the etching of formingthe through-hole structure, forming the PVX layer on the SD metal layercontinuously, performing a same etching as well, and finally forming theconductive film.

In order to solve the above-mentioned technical problem, the presentdisclosure further provides an array structure, which is manufactured bythe above-mentioned method for manufacturing an array structure.

In order to solve the above-mentioned technical problem, the presentdisclosure further provides a display device, which includes an arraysubstrate and a color filter substrate, and the array substrate isobtained by forming the above-mentioned array structure on a glasssubstrate.

In order to solve the above-mentioned technical problem, the presentdisclosure further provides a method for manufacturing an arraystructure, which method, after forming an SD metal layer on a GI layer,further includes: forming a through-hole structure in the SD metal layerto which a position where the SD signal access terminal is locatedcorresponds. Gradual slopes are formed on both sides of the through-holestructure.

Moreover, the through-hole structure includes a main hole andcompensation holes formed on both sides of the main hole. Thecompensation holes are smaller than the main hole. In addition, the mainhole is fully-transparent and the compensation holes are notfully-transparent.

Moreover, the through-hole structure includes a main hole andhalf-transparent films formed on both sides of the main hole. The mainhole is fully-transparent and the half-transparent films are notfully-transparent.

Moreover, the half-transparent films include a plurality of secondhalf-transparent films with different transmittances; and thetransmittances of the second half-transparent films are progressivelydecreased from the main hole as a start to the both sides.

Moreover, the through-hole structure provided with the main hole and thecompensation holes or with the main hole and the half-transparent filmsis formed in the SD metal layer by a wet etching. Subsequently, a layerof photoresist with a slope is formed on the SD metal layer. The heightof the photoresist is gradually reduced from the both sides to the mainhole. The photoresist is subjected to an exposure and the SD metal layeris subjected to a dry etching.

Furthermore, after performing the dry etching to the SD metal layer, themethod further includes: forming a PVX layer on the SD metal layer,performing a same slope etching to the PVX layer at a positioncorresponding to the through-hole structure, and finally forming aconductive film.

In order to solve the technical problem, the present disclosure furtherprovides an array structure, which is manufactured by theabove-mentioned method for manufacturing an array structure.

In order to solve the technical problem, the present disclosure furtherprovides a display device, which includes an array substrate and a colorfilter substrate, and the array substrate is obtained by forming thearray structure on a glass substrate.

Embodiments of the present disclosure provide an array structure, amanufacturing method thereof, an array substrate based on the arraystructure, and a display device, and before forming an SD metal layer ona GI layer, the method for manufacturing an array structure furtherincludes: etching the GI layer at a position corresponding to an SDsignal access terminal, and forming a through-hole structure in the GIlayer; or after forming an SD metal layer on a GI layer, the methodfurther includes forming a through-hole structure in the SD metal layerat a position corresponding to an SD signal access terminal, and in themethod, gradual slopes are formed on both sides of the through-holestructure. The GI layer beneath the SD metal layer is etched, so thatthe height of the conductive film on the SD metal layer can be reduced.Or the SD metal layer is etched to form the through-hole structureprovided with the gradual slopes on both sides thereof, so that the ITOlayers in the SD signal access terminal and the gate signal accessterminal in an alternate-wiring mode have same height, and hence theforces applied to conductive balls are more uniform and the conductivityis improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view of a gate layer and an SD layer which havewires thereof alternate with each other known by the inventor;

FIG. 2 is sectional views of a gate layer and an SD metal layer whichhave wires thereof alternate with each other known by the inventor;

FIG. 3 is sectional views of IC bonding pads of a gate layer and an SDmetal layer which have wires thereof alternate with each other known bythe inventor;

FIG. 4 is a flow chart of a method for manufacturing an array structure,provided by the embodiment 1 of the present disclosure;

FIG. 5 is a sectional view of an array structure provided by theembodiment 2 of the present disclosure;

FIG. 6 is a schematic view illustrating that IC pins and IC bonding padsare connected through an ACF in the embodiment 2 of the presentdisclosure;

FIG. 7 is a schematic view of an array substrate provided by theembodiment 2 of the present disclosure;

FIG. 8 is a sectional view of a mask applied in the embodiment 3 of thepresent disclosure;

FIG. 9 is a sectional view of a mask applied in the embodiment 3 of thepresent disclosure;

FIG. 10 is a schematic diagram illustrating a light distribution of amask applied in the embodiment 3 of the present disclosure;

FIGS. 11 to 13 are schematic views illustrating a process of forming athrough-hole structure provided with an inclined side wall in an SDlayer, in a method for manufacturing an array structure, provided by theembodiment 3 of the present disclosure;

FIG. 14 is a flow chart of the method for manufacturing the arraystructure, provided by the embodiment 3 of the present disclosure;

FIG. 15 is a sectional view of an array structure provided by theembodiment 4 of the present disclosure; and

FIG. 16 is a sectional view of an array substrate provided by theembodiment 4 of the present disclosure.

DETAILED DESCRIPTION

The technical solutions of the embodiments will be described in aclearly and fully understandable way in connection with the drawingsrelated to the embodiments of the disclosure. Apparently, the describedembodiments are just a part but not all of the embodiments of thedisclosure. Based on the described embodiments herein, those skilled inthe art can obtain other embodiment(s), without any inventive work,which should be within the scope of the disclosure.

Unless otherwise defined, all the technical and scientific terms usedherein have the same meanings as commonly understood by one of ordinaryskill in the art to which the present disclosure belongs. The terms“first,” “second,” etc., which are used in the description and theclaims of the present application for disclosure, are not intended toindicate any sequence, amount or importance, but distinguish variouscomponents. Also, the terms such as “a,” “an,” etc., are not intended tolimit the amount, but indicate the existence of at least one. Thephrases “connect”, “connected”, etc., are not intended to define aphysical connection or mechanical connection, but may include anelectrical connection, directly or indirectly. “On,” “under,” “right,”“left” and the like are only used to indicate relative positionrelationship, and when the position of the object which is described ischanged, the relative position relationship may be changed accordingly.

Embodiment 1

The embodiment of the present disclosure provides a method formanufacturing an array structure. Before the process of forming an SDmetal layer on a GI layer, the method further includes: etching the GIlayer at a position corresponding to an SD signal access terminal, andforming a through-hole structure in the GI layer.

In the method for manufacturing an array structure, before the processof preparing the SD metal layer, namely in the process of preparing theGI layer, the GI layer at a position corresponding to the SD signalaccess terminal (namely SD pad) is also subjected to same etchingtreatment. After etching, the increased height of the SD signal accessterminal can be eliminated, and hence the height difference between theconductive films (ITO) in the gate signal access terminal and the SDsignal access terminal can be reduced. Thus, the conductive films in thegate signal access terminal and the SD signal access terminal which areconnected to adjacent IC pins have a same height, so that the forcesapplied to conductive balls on the conductive films are more uniform andthe conductivity is improved.

For instance, in the embodiment, after the process of etching the GIlayer at the position corresponding to the SD signal access terminal (SDPad), the method further includes: forming a source/drain (SD) metallayer, a passivation (PVX) layer and a conductive film (ITO) in sequenceon the gate insulating (GI) layer provided with a through-holestructure.

Moreover, the process of forming the source/drain (SD) metal layer, thepassivation (PVX) layer and the conductive film (ITO) includes: etchingthe source/drain (SD) metal layer at a position corresponding to thethrough-hole structure in the GI layer, forming the passivation (PVX)layer on the source/drain (SD) metal layer continuously, etching the PVXlayer at a position corresponding to the through-hole structure in theGI layer, and finally forming the conductive film (ITO) on the PVXlayer.

FIG. 4 is a schematic flow chart of the method. As illustrated in FIG.4, the method specifically includes the following steps:

S1: forming a GI layer on a glass substrate;

S2: etching the GI layer at a position corresponding to the SD signalaccess terminal, and forming a through-hole structure; and

S3: forming an SD layer on the GI layer, etching the SD layer at aposition corresponding to the through-hole structure, forming a PVXlayer on the SD layer, etching the PVX layer at a position correspondingto the through-hole structure, and finally forming an ITO layer on thePVX layer.

The above steps are the processing flow of the SD signal accessterminal. The processing flow of the gate signal access terminal is asfollows: namely as illustrated in FIG. 2, forming a gate layer on aglass substrate 00, forming a gate electrode 01 by etching, forming a GIlayer 03 on the gate electrode 01, and etching the GI layer 03 at aposition corresponding to the gate electrode 01 to form a through hole;then forming a PVX layer on the GI layer 03 subsequently, and forming athrough hole at a position corresponding to the through hole by etching;and finally forming an ITO layer.

In the above method, partial GI layer 03 is etched at the positioncorresponding to the SD signal access terminal. When the SD metal layeris deposited, the SD metal layer in the SD signal access terminal iscloser to the surface of the glass substrate, and hence the effect ofincreasing the height of the conductive film on the GI layer 03 at theposition corresponding to the SD signal access terminal due to theexistence of the GI layer 03 can be relieved. Subsequently, thedeposition and etching of subsequent layers (namely the SD layer, thePVX layer and the conductive film) are performed, and finally the heightof the conductive film in the SD signal access terminal can be reduced.Thus, the height difference between the conductive films in the gatesignal access terminal and the SD signal access terminal can be reduced;the space uniformity between IC pins and IC bonding pads can beguaranteed; the forces applied to conductive balls between the IC pinsand the IC bonding pads can be more uniform; and hence the conductivitycan be improved.

Embodiment 2

The embodiment 2 of the present disclosure further provides an arraystructure manufactured by the manufacturing method provided by theembodiment 1 of the present disclosure, as illustrated in FIG. 5. Theleft side of the FIG. 5 and the left side of the FIG. 2 are identical,and both are a sectional view of a gate signal access terminal. Theright side of FIG. 5 is a sectional view of an SD signal accessterminal. The SD signal access terminal in the array structure providedby the embodiment 2 of the present disclosure includes a GI layer 103,an SD metal layer 102, a PVX layer 104 and a conductive film 105 formedin sequence; a through-hole structure is formed in the GI layer 103 at aposition corresponding to the SD metal layer 102; partial SD metal layer102 is formed in the through-hole structure; and the through-holestructure is provided with an outward-inclined side wall. Both the SDmetal layer 102 and the PVX layer 104 are provided with a concavityincluding an outward-inclined side wall at a position corresponding tothe through-hole structure, namely at a position corresponding to the SDsignal access terminal. Thus, the conductive film 105 is provided with aconcavity at a position corresponding to the SD signal access terminal.

FIG. 6 is a sectional view illustrating that a thin-film transistor(TFT) array substrate provided with the above-mentioned array structureand an IC are connected to each other through ACF (anisotropicconductive film). As illustrated in FIG. 6, IC pins Q1 on a TFTsubstrate U are connected to IC bonding pads Q2 through conductive balls106 in the anisotropic conductive film.

The embodiment further provides a display device, which includes anarray substrate and a color filter substrate. The array substrate isobtained by forming the array structure provided by the embodiment 2 ofthe present disclosure on a glass substrate.

FIG. 7 is a sectional view of the array substrate provided by theembodiment. As illustrated in FIG. 7, the array structure shown in FIG.5 is formed on a glass substrate 100.

The array substrate provided by the embodiment can achieve the reductionof the height difference between the conductive films in the gate signalaccess terminal and the SD signal access terminal, guarantee the spaceuniformity between IC pins and IC bonding pads, guarantee more uniformforces applied to the conductive balls between the IC pins and the ICbonding pads, and hence improve the conductivity.

Embodiment 3

The embodiment 3 of the present disclosure further provides a method formanufacturing an array structure. After the process of forming an SDmetal layer (SD layer) on a GI layer, the method further includes:forming a through-hole structure in the SD metal layer at a positioncorresponding to an SD signal access terminal. Gradual slopes are formedon both sides of the through-hole structure.

In the method, the SD layer is deposited after the GI layer is formed onthe glass substrate, and subsequently the SD layer at the positioncorresponding to the SD signal access terminal is etched. The method canalso reduce the height of the conductive film in the SD signal accessterminal, reduce the height difference between the conductive films inthe gate signal access terminal and the SD signal access terminal,guarantee the space uniformity between the IC pins and the IC bondingpads, guarantee more uniform forces applied to the conductive ballsbetween the IC pins and the IC bonding pads, and hence improve theconductivity.

In one example, as illustrated in FIG. 8, in the embodiment, a maskdesigned for forming the through-hole structure includes a main hole Aand compensation holes B1 and B2 formed on both sides of the main hole.A pore diameter of the compensation holes B1 and B2 is smaller than thatof the main hole A. In addition, the main hole A is fully-transparentand the compensation holes B1 and B2 are not fully-transparent. The porediameter of the compensation holes B1 and B2 is usually much smallerthan the resolution of an exposure machine. Light capable of runningthrough the compensation holes B1 and B2 on both sides can overlap andenhance the light running through the main hole A in the center.Meanwhile, the light intensity can be gradually reduced from the mainhole, as illustrated in FIG. 10.

In another example, as illustrated in FIG. 9, a mask includes a mainhole A and half-transparent films C1 and C2 formed on both sides of themain hole A. The main hole A is fully-transparent and thehalf-transparent films C1 and C2 are not fully-transparent.

For instance, the half-transparent films C1 and C2 include a pluralityof second half-transparent films with different transmittances. In theexample as shown in FIG. 9, the half-transparent films C1 and C2 includethree-level second half-transparent films with different transmittances,namely the half-transparent film C1 includes three secondhalf-transparent films C11 to C13 with different transmittances and thehalf-transparent film C2 includes three second half-transparent filmsC21 to C23 with different transmittances. Moreover, the transmittancesof the half-transparent films C11 to C13 and C21 to C23 areprogressively decreased from the main hole A in the center to bothsides, namely the transmittances of C13, C12 and C11 are decreasedprogressively and the transmittances of C23, C22 and C21 are alsodecreased progressively. This design of the main hole and thehalf-transparent films can guarantee that the light intensity can notrapidly reduce from the main hole, but gradually reduce from the mainhole to both sides, namely the light intensity reduces gradually, asillustrated in FIG. 10.

For instance, by adoption of the mask including the main hole and thecompensation holes or the main hole and the half-transparent films, thethrough-hole structure is formed in the SD metal layer at the positioncorresponding to the SD signal access terminal by photolithography and awet etching. Gradual slopes are formed on both sides of the through-holestructure. As illustrated in FIG. 11, an SD metal layer 202 is formed ona GI layer 203, and a photoresist PR is formed on the SD metal layer202. By adoption of the mask as shown in FIGS. 8 and 9 forphotolithography, the photoresist PR provided with the slopes is formedon the SD metal layer 202, namely the photoresist PR at a positioncorresponding to the main hole of the mask is removed and thephotoresist PR provided with the slopes is formed on both sides of theposition. Subsequently, a wet etching is performed and a through hole isformed in the SD metal layer 202, as illustrated in FIG. 12.Subsequently, a dry etching process is performed to the photoresist PRand the SD metal layer 202. As the photoresist PB on the periphery ofthe through hole in the SD layer 202 has a slope shape, after thesimultaneous dry etching of the photoresist PR and the SD metal layer202, a side wall of the through hole formed in the SD layer 202 is alsoprovided with a similar gradual slope structure, as illustrated in FIG.13. As the through hole of the SD metal layer 202 at the positioncorresponding to the SD signal access terminal is provided with a sidewall including a gradual slope, the height of the conductive ball formedon the through hole is reduced; the space uniformity between the IC pinand the IC bonding pad is guaranteed; the contact area between theconductive ball and the conductive film is also increased; the contactarea between the conductive film and the SD metal layer is alsoincreased; and hence the conductivity is better.

For instance, after the dry etching process for the SD metal layer, themethod further includes: forming a PVX layer on the SD metal layer,forming a through hole with a same inclined side wall in the PVX layerat a position corresponding to the through-hole structure in the SDmetal layer, and finally forming a conductive film on the through hole.

FIG. 14 is a flow chart of the method provided by the embodiment. Themethod specifically includes the following steps.

S1′: forming a GI layer on a glass substrate;

S2′: forming an SD layer on the GI layer, performing a wet etching and adry etching on the SD layer, and forming a through-hole structureprovided with an outward-inclined side wall at a position correspondingto an SD signal access terminal; and

S3′: forming a PVX layer on the SD layer, forming a through-holestructure provided with an outward-inclined side wall in the PVX layerat a position corresponding to the through-hole structure, and finallyforming a conductive film on the through-hole structure.

The process of processing one side of the gate signal access terminal inthe embodiment is the same with that of the embodiment 1. Thus, detaileddescription will be omitted herein.

In the method, as the through hole in the SD metal layer 202 at theposition corresponding to the SD signal access terminal is provided witha side wall including a gradual slope, the height of the conductive ballformed on the through hole is reduced; the space uniformity between theIC pin and the IC bonding pad is guaranteed; the forces applied to theconductive balls between the IC pins and the IC bonding pads are moreuniform; and hence the conductivity is improved. Moreover, the contactarea between the conductive ball and the conductive film is increased;the contact area between the conductive film and the SD metal layer isalso increased; and hence the conductivity is better.

Embodiment 4

The embodiment 4 of the present disclosure further provides an arraystructure manufactured by the manufacturing method provided by theembodiment 3 of the present disclosure, as illustrated in FIG. 15. Theleft side of FIG. 15 and the left sides of FIGS. 2 and 5 are identical,and each is a sectional view of a gate signal access terminal. The rightside of FIG. 15 is a schematic sectional view of an SD signal accessterminal. The SD signal access terminal in the array structure providedby the embodiment 4 of the present disclosure includes a GI layer 203,an SD metal layer 202, a PVX layer and a conductive film 205 formed insequence. A through-hole structure is formed in partial SD metal layer202.

Moreover, the embodiment further provides a display device, whichincludes an array substrate and a color filter substrate. The arraysubstrate is obtained by forming the array structure provided by theembodiment 4 of the present disclosure on a glass substrate 200.

The array substrate provided by the embodiment can reduce the heightdifference between the conductive films in the gate signal accessterminal and the SD signal access terminal, guarantee the spaceuniformity between the IC pins and the IC bonding pads, guarantee moreuniform forces applied to the conductive balls between the IC pins andthe IC bonding pads, and hence improve the conductivity.

The foregoing embodiments are only intended to illustrate the presentdisclosure but not intended to limit the present disclosure. Variousmodifications and variations may also be made by those skilled in theart without departing from the spirit and scope of the presentdisclosure. Thus, all the equivalent technical solutions should bewithin the scope of the present disclosure. The scope o of the presentdisclosure shall be defined by the claims.

The application claims priority to the Chinese Patent Application No.201310571411.1 filed on Nov. 15, 2013. The disclosure content of theChinese Patent Application is incorporated herein as part of theapplication.

What is claimed is:
 1. A method for manufacturing an array structure,comprising: forming a gate insulating layer on a substrate; and etchingthe gate insulating layer at a position corresponding to a source/drainsignal access terminal to form a through-hole structure provided with anoutward-inclined side wall in the gate insulating layer.
 2. The methodfor manufacturing the array structure according to claim 1, furthercomprising: forming a source/drain layer on the gate insulating layerand at a position corresponding to the through-hole structure of thegate insulating layer, wherein a concavity provided with anoutward-inclined side wall is formed in the source/drain layer at theposition corresponding to the through-hole structure of the gateinsulating layer.
 3. The method for manufacturing the array structureaccording to claim 2, further comprising: forming a passivation layer onthe source/drain layer and etching the passivation layer; and forming aconductive film on the passivation layer, wherein the passivation layeris provided with a through-hole structure which comprises anoutward-inclined side wall at the position corresponding to thethrough-hole structure of the gate insulating layer.
 4. The method formanufacturing the array structure according to claim 3, wherein theconductive film is electrically connected with the source/drain layer atthe position corresponding to the through-hole structure of the gateinsulating layer.
 5. The method for manufacturing the array structureaccording to claim 3, further comprising: forming another conductivefilm at a position corresponding to a gate signal access terminal,wherein the conductive film and the another conductive film have a sameheight on the substrate.
 6. An array structure, comprising: a substrate;and a gate insulating layer provided on the substrate and provided witha through-hole structure which comprises an outward-inclined side wall.7. The array structure according to claim 6, further comprising asource/drain layer formed on the gate insulating layer and provided witha concavity which comprises an outward-inclined side wall at a positioncorresponding to the through-hole structure of the gate insulatinglayer.
 8. The array structure according to claim 7, further comprising:a passivation layer formed on the source/drain layer and provided with athrough-hole structure which comprises an outward-inclined side wall atthe position corresponding to the through-hole structure of the gateinsulating layer; and a conductive film formed on the passivation layer.9. The array structure according to claim 8, wherein the conductive filmis electrically connected with the source/drain layer at the positioncorresponding to the through-hole structure of the gate insulatinglayer.
 10. The array structure according to claim 8, further comprising:another conductive film at a position corresponding to a gate signalaccess terminal, wherein the conductive film and the another conductivefilm have a same height on the substrate.
 11. An array structure,comprising: a gate insulating layer provided on a substrate; and asource/drain layer provided on the gate insulating layer and providedwith a through-hole structure which comprises an outward-inclined sidewall.
 12. The array structure according to claim 11, further comprising:a passivation layer formed on the source/drain layer and provided with athrough-hole structure, which comprises an outward-inclined side wall,at a position corresponding to the through hole of the source/drainlayer; and a conductive film formed on the passivation layer.
 13. Thearray structure according to claim 12, wherein the conductive film iselectrically connected with the source/drain layer at the positioncorresponding to the through-hole structure of the source/drain layer.14. The array structure according to claim 12, further comprising:another conductive film at a position corresponding to a gate signalaccess terminal, wherein the conductive film and the another conductivefilm have a same height on the substrate.